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XMEGA A [MANUAL]
8077I–AVR–11/2012
Notes:
1.
This option should be used only when frequency stability at startup is not important for the application. The option is not suitable for crystals.
2.
This option is intended for use with ceramic resonators. It can also be used when the frequency stability at startup is not important for the
application.
3.
When the external oscillator is used as the reference for a DFLL, only EXTCLK and 32KHZ can be selected.
7.10.4 XOSCFAIL – XOSC Failure Detection register
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure is detected. Writing logic
one to this location will clear XOSCFDIF.
Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when XOSCFDIF is
set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on
page 13 for details. Once enabled, failure detection can only be disabled by a reset.
7.10.5 RC32KCAL – 32kHz Oscillator Calibration register
Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration bits
This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is loaded from the signature
row of the device and written to this register during reset, giving an oscillator frequency close to 32.768kHz. The register
can also be written from software to calibrate the oscillator frequency during normal operation.
7.10.6 PLLCTRL – PLL Control register
0011
XTAL_256CLK(1)
0.4MHz - 16MHz XTAL
256 CLK
0111
XTAL_1KCLK(2)
0.4MHz - 16MHz XTAL
1K CLK
1011
XTAL_16KCLK
0.4MHz - 16MHz XTAL
16K CLK
XOSCSEL[3:0]
Group Configuration
Selected Clock Source
Start-up Time
Bit
7654
3
2
1
0
+0x03
–
XOSCFDIF
XOSCFDEN
Read/Write
RRRR
R
R/W
Initial Value
0000
0
Bit
7
6543
210
+0x04
RC32KCAL[7:0]
Read/Write
R/W
Initial Value
x
xxxx
xx
Bit
7
6
543
210
+0x05
PLLSRC[1:0]
–
PLLFAC[4:0]
Read/Write
R/W
R
R/W
Initial Value
0
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